Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the subear-threshold regime

摘要

Subear-threshold computing has been proposed for ultra-low power applications. FinFET devices are considered as an alternative for bulk CMOS devices due to the superior characteristics, which make FinFET an excellent candidate for ultra-low power designs. In this paper, we first present an improved analytical FinFET model covering both sub- and near-threshold regimes. This model accurately captures the drain current as a function of both the gate and drain voltages. Based on the accurate FinFET model, we provide a detailed analysis on stack sizing of FinFET logic cells, and derive the optimal stack depth in FinFET circuits. We also provide a delay optimization framework for the FinFET circuits in the subear-threshold region, based on the stack sizing analysis. To the best of our knowledge, this is the first work that provides in-depth analysis of the stack sizing of FinFET logic cells in the subear-threshold region based on the accurate FinFET modeling. Experimental results on the 32nm Predictive Technology Model for FinFET devices demonstrate the effectiveness of the proposed optimization framework.