HIGH FREQUENCY PROGRAMMABLE WIDE-BAND FREQUENCY DIVIDER DESIGN FOR CMOS SOFTWARE DEFINED RADIO TRANCEIVERS

摘要

This paper presents the analyses, design and measurement results of a high frequency programmable frequency divider. The circuit is used in a monolithic wideband reconfigurable direct conversion quadrature transceiver. The divider provides the up and down conversion mixers with the quadrature LO signals. The divider operates at only 1.5 V, making it an ideal choice for low-power mobile applications. The circuit is fabricated in a 0.13 μm standard analog CMOS technology.