This paper describes a new architecture for lock-detect circuit that is used in self correcting DLLs. Using this architecture solves the false locking problem of conventional DLLs. The operation of proposed architecture does not depend on the duty cycle of the input phases. The proposed lock-detect circuit is used in a wide frequency range and low jitter delay-locked loop. The circuit design and ADS simulation are based upon TSMC 0.18μm CMOS process. The simulation results show that the proposed DLL has a wide locking range from 120 to 420 MHz. Moreover rms jitter is as low as 1.2 ps at 420 MHz.
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