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Solder/adhesive bonding using simple planarization technique for 3D integration

机译:使用简单的平面化技术进行3D集成的焊锡/粘合剂粘结

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This paper describes a hybrid solder/adhesive bonding method using a simple planarization technique for three-dimensional (3D) integration. With the hybrid bonding method, the chip bonding and encapsulation of underfill resin between chips is completed in one step. The simple planarization technique is used to planarize adhesive on a flat Si substrate coated with a release agent. The planarization technique is a simple and inexpensive operation compared to the conventional processes using Chemical Mechanical Polishing (CMP) or fly cutting. Since the CMP process has advantages for wafer-level fabrication, we also evaluated hybrid bonding using CMP. The results of the simple planarization process show that the spaces around the Cu/Sn bumps were fully filled with the adhesive, and the adhesive residual layer on the Cu/Sn bumps was removed by O2 plasma. A cross-sectional SEM image after the hybrid bonding using the proposed planarization process shows that the Cu/Sn solder had properly wetted the Au and the adhesive had uniformly filled the small gaps between the bonded chips. Solder/adhesive bonding using CMP was also succeeded. In addition, Au/adhesive bonding with 10-μm pitch Au bumps was realized.
机译:本文介绍了一种使用简单的平面化技术进行三维(3D)集成的混合焊料/粘合剂粘结方法。通过混合键合方法,一步完成芯片之间的键合和底部填充树脂的封装。简单的平坦化技术用于使涂有脱模剂的平坦Si基板上的粘合剂平坦化。与使用化学机械抛光(CMP)或飞刀切割的常规工艺相比,平面化技术是一种简单且廉价的操作。由于CMP工艺对于晶圆级制造具有优势,因此我们还评估了使用CMP的混合键合。简单平面化过程的结果表明,Cu / Sn凸块周围的空间已被粘合剂完全填充,并且通过O 2 等离子体去除了Cu / Sn凸块上的粘合剂残留层。使用建议的平坦化工艺进行混合键合后的横截面SEM图像显示,Cu / Sn焊料已适当润湿了Au,并且粘合剂均匀地填充了键合芯片之间的小间隙。使用CMP的焊锡/胶粘剂粘接也成功了。另外,实现了具有10μm间距的Au凸块的Au /粘合剂键合。

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