首页> 外文会议>2011 IEEE 29th International Conference on Computer Design >Towards a tool for implementing delay-free ECC in embedded memories
【24h】

Towards a tool for implementing delay-free ECC in embedded memories

机译:迈向在嵌入式存储器中实现无延迟ECC的工具

获取原文

摘要

The reliability of modern Integrated Circuits is affected by nanometric scaling. In many modern designs embedded memories occupy the largest part of the die and are designed as tight as allowed by the process. So they are more prone to failures than other circuits. Error correcting codes (ECC) are a convenient mean for protecting memories against failures. A major drawback of ECC is the speed penalty induced by the encoding and decoding circuits. In [5], we propose an architecture eliminating ECC delays in both read and write paths. However, this previous work does not describe a generic set of rules enabling inserting the delay-free ECC in any design. In this paper, we present the key points of an algorithm and a related tool automating its implementation.
机译:现代集成电路的可靠性受纳米尺度的影响。在许多现代设计中,嵌入式存储器占据了芯片的最大部分,并且设计得尽可能严格。因此,它们比其他电路更容易出现故障。纠错码(ECC)是防止内存故障的一种便捷方式。 ECC的主要缺点是编码和解码电路引起的速度损失。在[5]中,我们提出了一种消除读写路径中ECC延迟的架构。但是,此先前的工作没有描述允许在任何设计中插入无延迟ECC的通用规则集。在本文中,我们介绍了一种算法的关键点以及实现其自动化的相关工具。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号