Reconfigurable Fault-Tolerant System Sychronization

摘要

A method and architecture for synchronization of Fault-Tolerant system implemented in FPGAs is proposed. It is based on repairing faulty units and transferring of the fault-free state of the system to the unit under repair. Its architecture is based on the previously designed model which is extended for usage in more complex systems. The proposed method was implemented on an FPGA and the experimental architecture with an analysis of the results is given.