首页> 外文会议>Intelligent Systems, Modelling and Simulation (ISMS 2010), 2010 >A 2.4GHz 1.8-V CMOS Sub-harmonic Mixer with Inherent Harmonic-Rejection
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A 2.4GHz 1.8-V CMOS Sub-harmonic Mixer with Inherent Harmonic-Rejection

机译:具有固有谐波抑制功能的2.4GHz 1.8V CMOS次谐波混频器

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This paper presents a novel low power high linear sub-harmonic mixer for direct-down conversion receivers, in which an inductive connection between RF and LO stages is proposed to improve the linearity and enhance the gain of Mixer. This is a novel mixer that not only frequency translates the RF signal to baseband directly but also avoids the need for a discrete filter by attenuating the third and fifth harmonics using the harmonic rejection structure. The proposed core uses 1/2 × LO generation scheme to overcome LO self-mixing and IMD2 related problems common in conventional Direct Conversion Receivers. Simulation results performed by Advanced Design System (ADS) in 0.18 ¿m TSMC CMOS process show a voltage conversion gain of 15.57 dB, an overall double side band noise figure of 6.88 dB, input referred 1 dB compression point of -11.5 dBm and IIP3 of 1.5 dBm while draining 4.2 mA from 1.8 V supply.
机译:本文提出了一种适用于直接下变频接收器的新型低功率高线性次谐波混频器,其中提出了RF级与LO级之间的电感连接,以改善线性度并提高混频器的增益。这是一种新颖的混频器,它不仅可以将射频信号直接频率转换为基带,而且还可以通过使用谐波抑制结构衰减三次谐波和第五次谐波来避免使用分立滤波器。拟议的内核使用1/2ƒLO生成方案,以克服传统直接转换接收器中常见的LO自混和与IMD2相关的问题。由先进设计系统(ADS)在0.18μm的TSMC CMOS工艺中执行的仿真结果显示,电压转换增益为15.57 dB,整体双边频带噪声系数为6.88 dB,输入参考为1 dB压缩点-11.5 dBm的IIP3和1.5 dBm的IIP3,同时从1.8 V电源消耗4.2 mA的电流。

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