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Finite element stress analysis of an multi-chip package by Taguchi design of experiments for package component thicknesses

机译:Taguchi设计的多芯片封装有限元应力分析,用于测试封装组件的厚度

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Slacked multi-chip package (MCP) has been an increasingly important approach for realizing high-density 3D packaging. To accommodate multiple chips within a standard package height with adequate integrity and reliability puts stringent demands on wafer thinning technology, as well as on assembly process technology. In this work, internal stress distribution and package warpage in MCP originated from process thermal load have been systematically investigated as functions of all structure parameters by finite element analysis (FEA) and Taguchi design of experiments (DOE). It is found that top die is the easiest to crack under thermal stress. The maximum stress in this die can be effectively relieved by increasing its thickness and/or by decreasing the thickness of die attach underneath. Shear stress at each interface depends negatively on the corresponding die attach thickness, while top-surface warpage can be controlled by mould compound thickness above top die.
机译:松弛的多芯片封装(MCP)已经成为实现高密度3D封装的越来越重要的方法。为了在标准封装高度内容纳多个芯片并具有足够的完整性和可靠性,对晶圆薄化技术以及组装工艺技术提出了严格的要求。在这项工作中,通过有限元分析(FEA)和Taguchi实验设计(DOE),系统地研究了源自过程热负荷的MCP中内部应力分布和封装翘曲,作为所有结构参数的函数。发现顶部模具在热应力下最容易破裂。可以通过增加其厚度和/或减小其下方的管芯附着厚度来有效地缓解该管芯中的最大应力。每个界面处的剪切应力均与相应的芯片附着厚度负相关,而顶面翘曲则可通过顶模上方的模塑料厚度来控制。

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