This paper introduces an analog self-calibration algorithm for multi-bit per stage pipelined ADCs. The algorithm employs a high accuracy DAC to serve as the sub-DAC and to calibrate the error introduced by the sub-ADC, sub-DAC and partial effect of the interstage gain amplifier errors. Simulations of a 10-bit 3-stage pipelined ADC demonstrate that the algorithm dramatically improves the static and dynamic performance of the ADC.
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