A predictive phase locked loop applicable to utility and non-utility AC power systems

摘要

A predictive phase locked loop (PPLL) suitable for applications in utility and non-utility power systems and power electronics is presented. The PPLL is frequency adaptive and can provide time variant information about the frequency and amplitude of the fundamental component of an input signal. The PPLL offers a high degree of immunity to wide-band noise, harmonics, inter-harmonics and impulse disturbances. Analytical methods for modeling the PPLL are developed to achieve high execution speed and low real-estate utilization. The mathematical properties of the analytical methods are presented. The PPLL is implemented on a field programmable gate array (FPGA). The locking range of the PPLL is from a fraction of Hz to a few kHz and from 3% to 100% of the nominal input amplitude. The worst case response time of the PPLL is 2 cycles of the input signal period for any realistic perturbation in frequency, amplitude, and/or phase angle. The proposed method is faster, more flexible and more robust than currently available methods.