AR AR /SO T AR CO- SI O A AVA CO-PROC SSOR OR A 3 -BIT RISC S ST MA T IMP M TATIO O T AR AR PARTITIO

摘要

In this paper we proposed a design of a Java co-processor for a 32-bit RISC system to improve its performance, as the software only Java interpreter is more time-consuming. Our work includes the hardware/software co-design of the Java Card Virtual Machine (JCVM) and the details of its hardware implementation. The JCVM translates the Java bytecodes (JBCs) into the native RISC instructions and then passes them to the RISC core. A 16-byte pre-fetch FIFO and the folding mechanism are applied to further speedup the translation.