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Power-optimal simultaneous buffer insertion/sizing and wire sizing

机译:功率最佳的同时缓冲区插入/大小调整和电线大小调整

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This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty. We derive closed form optimal solutions for both cases. These closed form solutions can be used to efficiently estimate the power dissipation in the early stages of the VLSI designs. We observe that the power dissipation can be much different even with the same optimal delay.
机译:本文研究了通过同时考虑缓冲区插入/大小调整和电线大小调整(BISWS)来使互连电线的功耗最小化的问题。我们考虑两种情况,即以最佳延迟约束最小化功耗,并以给定的延迟代价最小化功耗。我们针对这两种情况得出封闭形式的最优解。这些封闭形式的解决方案可用于在VLSI设计的早期阶段有效地估计功耗。我们观察到,即使具有相同的最佳延迟,功耗也会有很大差异。

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