The derivation of minimal test sets for combinational logic circuits using genetic algorithms

摘要

To reduce the post-production cost of testing digital circuits, the derivation of minimal test sets is an important issue. The technique presented here applies a genetic algorithm to find minimal or near minimal test sets. The algorithm aims to minimise test sets that have been previously generated by an ATPG system and as such has been designed as a post-processor. The algorithm has been applied to a family of RISC (Reduced Instruction Set Computer) processors and a selection of ISCAS-85 benchmark circuits.