This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.
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机译:本文介绍了CMOS宏观设计中互补通晶体管逻辑(CPL)电路的设计和实现。评估通过晶体管逻辑电路的电源,速度和噪声裕度,晶体管尺寸针对噪声裕度和电路性能进行了优化。该电路已成功实现在IBM S / 390 CMOS处理器中的64位纠错码(ECC)和奇偶校验宏中,并显着提高了ECC宏观性能的功率和速度。
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