Improved method for the oxide thickness extraction in MOS structures with ultra-thin gate dielectrics

摘要

An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique (Maserjian et al., Solid State Electron. vol. 17, pp. 335-9, 1974) and of Vincent's method (Vincent et al., Proc. IEEE Microelectronic Test Structures vol. 10, pp. 105-10, 1997) is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm down to 1.8 nm.