In semiconductor manufacturing, front end scaling (i.e. Moore's Law) continues to hold for the forseeable future. Unfortunately, the back-end processes of package assembly, burn-in and test all require wafer singulation before any of these processes can occur. Singulation immediately forces a linearly increasing cost model, scaling with the number of die/wafer, and prevents a wafer scaling cost model. FormFactor looked at the issues preventing wafer-level back-end processing, and postulated that the highest probability of success would require an approach that integrated the previously separate disciplines of materials, package assembly, burn-in, and test. The connection element to the test and burn-in systems was identified as a primary enabler or inhibitor. In this paper, we briefly describe a wafer-level back-end flow, the chip scale package that this process defines, and the early results observed with this flow and package.
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