Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

摘要

Using strained SiGe on Si, the threshold voltage of high 驴 PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high 驴 and metal gates for 32nm node and beyond.