NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration

摘要

The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex embedded applications performance requirements. Due to the increasing scale of embedded systems bus-based communication no longer meet bandwidth requirements and therefore networks-on-chip (NoC) are increasingly used to process communication in embedded parallel applications. So far, neither development environments and tools for embedded systems nor profiling and debugging techniques of embedded systems tackled the issue of network on chip monitoring. Due to the complexity of future multiprocessors systems on chip parallel programmers will unavoidably need to be able to get accurate profiles of communication patterns on various network on chip links and this in order to optimize their applications through timing analysis, timing predictability, and real-time scheduling analysis. We propose in this paper a scalable network on chip real time hardware monitoring feedback for multiprocessors systems on chip parallel programmers. Implementation of our scheme for a 2x2 mesh based multiprocessor systems on chip demonstrates the validity of our approach for an image processing application.