Asynchronous array multiplier with an asymmetric parallel array structure

摘要

In this paper an asynchronous array multiplier with a new parallel structure is introduced. This parallel array structure is designed to make the computation time faster with lower power consumption. An asymmetric array structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional Booth encoding array structures and that the multiplier with the proposed array structure shows reduction of 40% in the computational time with relatively lower power consumption.