Thermal management estimations for buried bump interconnection technology printed wiring boards with bump (filled via) interconnection

摘要

We have developed B/sup 2/it (buried bump interconnection technology) printed wiring boards (PWBs) for high density and high performance requirements. Semiconductor devices are attaining higher operating speeds and higher integration, and PWBs thus require improved thermal management properties. Conventional PWBs have low thermal conductivity compared with ceramic substrates, etc. The B/sup 2/it PWBs have filled via holes using Ag paste bumps to connect wiring lines between neighbouring layers. This feature is different from conventional PWBs with copper-plated through holes. The manufacturing process for B/sup 2/it PWBs is also unique and simple because the bumps are formed by printing and interconnections between layers are formed by lamination without drilling and plating. The filled via holes can become thermal via holes for improved heat radiation. The thermal conductivity of the via hole material is useful for designing the B/sup 2/it PWBs. This paper reports the thermal properties of the B/sup 2/it PWBs by measuring the thermal resistance of various filled via hole samples. The thermal resistance was calculated from measurement of the temperature difference between the sample surfaces using an original measurement system, and the thermal conductivity of the via hole material was simulated from the measured values. As a result, the thermal conductivity of the via hole material was found to be very high compared with that of the normal printed Ag paste, and the B/sup 2/it PWBs had thermal management properties which were good enough for high density packaging.