CMOS gate array architecture for digital signal processing applications

摘要

A CMOS gate array architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate arrays.