Validatable nonrobust delay-fault testable circuits via logic synthesis

摘要

Necessary and sufficient conditions for validatable nonrobust delay-fault testability of paths in arbitrary, multilevel networks are given. Validatable nonrobust testing, as opposed to robust testing, offers degrees of freedom that enable the development of efficient synthesis procedures that target delay-fault testability, and also provides a means of producing compact test vector sets. Synthesis procedures that produce networks that are fully testable under the validatable nonrobust fault model are developed. It is shown that primality and irredundancy is both a necessary and sufficient condition for complete validatable nonrobust testability in the two-level case. It is proven that synthesizing a multilevel network using algebraic factorization retains complete validatable nonrobust testability. Preliminary experimental results, which indicate that completely validatable nonrobust testable networks can be synthesized with small area overheads using the presented synthesis procedures, are provided.