A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool

摘要

This paper presents a new folding algorithm applied to an automatic layout generation tool. Most of transistors sizing algorithms propose continuous sizing. Nevertheless, in row-based layout synthesis, the variation of transistor sizes may cause non-uniform cell heights that may lead to significant waste of layout area. The proposed folding approach leads to a very simple algorithm that is able to obtain very good results.