Optimal Processor Mapping Scheme for Efficient Communication of Data Realignment

摘要

In this paper, we present an Optimal Processor Mapping (OPM) scheme to minimize data transmission cost for general BLOCK-CYCLIC data realignment. We examine a size oriented greedy matching method and the maximum bipartite matching theory to explore logical processor sequences. Based on these matching polices, the realigned sequences are used to perform data realignment in the destination phase. A significant improvement of our approach is that the OPM achieves high ratio of data remain in local space and leading minimum inter-processor communications. The OPM scheme could handle array realignment with arbitrary BLOCK-CYCLIC type and multidimensional arrays. Theoretical analysis and experimental results show that our technique provides considerable improvement for dynamic data realignment.