Multi-Stage Interconnection Network Recursive-Clos(R-Clos)II: A Scalable Hierarchical Network for A Compiler Directed Multiprocessor ASCA

摘要

In 1998, we proposed a multistage interconnection network Recursive-Clos(R-Clos) for a multiprocessor ASCA to schedule the data transfer statically. R-Clos consists of hierarchically clustering multiple Clos networks with extra intermediate stages. To improve the transfer ability between layers of R-Clos, we modify R-Clos, and modified R-Clos is named R-Clos II. R-Clos II provides multiple paths to other level-1 cluster, while R-Clos does only one path. A basic scheduling schemes on R-Clos II and a heuristic scheduling schemes for level-1 (Clos) network are also introduced. A switch chip of R-Clos II was fabricated on 0.35 μm gate array with dedicated switch architecture for the static packet scheduling. The average latency of this switch chip is 40% lower than that of an usual single channel input queuing switch. To compare R-Clos II with the original R-Clos, the throughput and the latency are also analyzed with computer simulation. The hardware cost of R-Clos II are only 8% larger than that of R-Clos.