Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration

摘要

This paper discusses how to perform online integrity checking for a clock system spanning all over a heterogeneously integrated IC. A clock system in this work is assumed to consist of two major components - (1) the Delay-Locked Loop (DLL), commonly used for module-to-module clock synchronization, and (2) the clock distribution network (with clock buffers and interconnects). For the DLL part, we incorporate a “phase error monitoring scheme”, which is able to detect abnormal safety hazard, e.g., an instantaneous power glitch. For the clock distribution network, we incorporate a periodic self-test scheme featuring a “special short-pulse driven flush test procedure” to detect any worsening Clock Delay Fault (CDF). The proposed method can help identify a failure threat before it strikes havoc. Post-layout simulation results are presented to demonstrate the effectiveness of the proposed schemes.