Applications of Hierarchical Test

摘要

Advanced technology nodes enable chip designs to have more functionality and more complexity, but are more prone to manufacturing defects due to smaller dimensions. Hierarchical test is a recent partitioned-test method designed to ease computing resources and run times required for automatic test pattern generation (ATPG) on very large designs. This paper discusses the general architecture and details of our implementation, including improved parallel testing of identical logic blocks. Results from three production designs, presented as a case study, show the benefits of using hierarchical test on very large designs.