Design of a CMOS Low-Power Limiting Amplifier with RSSI Integrated Circuit for Low-Frequency Wake-Up Receivers

摘要

This paper presents the circuit level design of a CMOS low power limiting amplifier with received signal strength indicator (RSSI) for low frequency application. The design utilizes a five-stage cascade amplifier with PMOS double diode-connected load for the limiting amplifier and a successive detection log amp for the RSSI structure. DC feedback technique is employed to suppress the DC offset at the output. The proposed circuit is laid out in 0.13 μm CMOS technology, then extracted and simulated. It occupies a minimal active area of 0.0084 mm