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Programmable Gain and Bandwidth Op-Amp Using Controllable Input Stage Tail Current

机译:使用可控输入级尾电流实现可编程增益和带宽运算放大器

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This paper presents a novel technique to design a programmable open-loop DC gain and bandwidth single-ended output CMOS (complementary metal oxide semiconductor) opamp (operational amplifier) using a serial digital interface. The circuit topology allows for the programming of the differential input stage tail current. With this variable tail current, a controllable open-loop DC gain and frequency response is created that can be controlled from a host digital processor. The op-amp circuit has a rail-to-rail output where the first stage of the op-amp consists of differential input and folded-cascode circuits that are compensated using a negative Miller capacitor, and the second stage is a class-AB amplifier compensated by a conventional Miller capacitor. The op-amp has been designed using a 0.35 μm CMOS technology, its operation simulated using the Cadence Spectre simulator and operates on a single-rail +3.3V power supply.
机译:本文提出了一种新颖的技术,可使用串行数字接口设计可编程的开环DC增益和带宽单端输出CMOS(互补金属氧化物半导体)运算放大器(运算放大器)。电路拓扑允许对差分输入级尾电流进行编程。利用这种可变的尾电流,可以创建可控的开环DC增益和频率响应,可以从主机数字处理器进行控制。运算放大器电路具有轨到轨输出,其中运算放大器的第一级包含差分输入和折叠共源共栅电路,并使用负米勒电容器进行补偿,而第二级则是AB类放大器由传统的米勒电容器补偿。该运算放大器采用0.35μmCMOS技术进行设计,其操作使用Cadence Spectre模拟器进行仿真,并使用+ 3.3V单轨电源供电。

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