A Field Programmable Gate Array (FPGA) Implementation of a Counter-Based Lossless Data Compression

摘要

High-performance lossless data compression can be implemented in a field programmable gate array (FPGA)-based integrated circuit (IC) achieving a trough-put of more than 1.5 Mbit/s. Such a high performance is due to a new architecture based on simple counters, implementing a compression method developed by R. F. Rice. This Rice coder peforms comparably to Huffman and arithmetic coders. However, Rice coder is designed for certain entropy ranges that are of interest. Hence, simple counters can be used to realize the coder, consuming resources less than 70% of a single FPGA XC4005 only for both the encoder and the decoder.