Novel Approach for Sleep Transistor Sizing to Suppress Power and Ground Bouncing Noise in MTCMOS Clustering Technique

摘要

In this paper, different sizes of sleep transistors with an increasing number of inverters using clustering technique are presented. Simulation result shows that delay is reduced up to 0.68 times when the width-to-length ratio is increased by 10 times in the circuit. Dynamic power is increased up to 1.24 times when W/L ratio is increased by 10 times in circuit; leakage power is increased up to 1.54 times when size is increased by 10 times in circuit; wakeup time is reduced up to 0.52 times when size is increased by 10 times in circuit; and sleep time is reduced up to 0.75 times when size is increased by 10 times in the clustering circuit.