Designing a tiny and customizable TCP/IP core for low cost FPGA

摘要

The aim of this project is to develop a tiny and flexible hardware TCP/IP module. The module is so autonomous and so lightweight that can fits in low cost FPGA. In this project, the different communication layers responsible for robust and sturdy internet connectivity are investigated. Starting from a handful set of elementary idea, a customizable and basic hardware TCP/IP stack is designed. For this project, a bottom-up strategy is adopted. It starts by the Ethernet module up to the TCP unit.