Modeling, design and analysis of high CMRR two stage gate driven operational transconductance amplifier using 0.18 μm CMOS technology

摘要

Design of analog circuit is mainly based on simulations that are strongly dependent on EDA tools and competency of the designer. With regard to this, the automatic designs automation for analog architectures is required to solve the simulation time problem. This paper deals with the method for modeling the analog architecture to evaluate the performance parameters; this is for optimizing the transistor size to achieve the desired characteristics. Finally the proposed methodology is applied to design a gate driven Operational Transconductance Amplifier (OTA) using TSMC 0.18 μm CMOS Technology and the design evaluation is done in Cadence Virtuoso. Then, we analyze the performance parameters of the proposed OTA according to the desired specification at 0.18 μm CMOS Technology. This proposed OTA has a supply Voltage of 1.6 V. The multifunction filter is also implemented using OTA of 2.5 V supply.