Circuit segmentation using GP in FPGA's technology mapping

摘要

In this paper an algorithm for efficient technology mapping in FPGAs using circuit segmentation is proposed and implemented. In this paper area minimization of the circuit along with the optimal use of Table Look Ups (TLU) in the existing library, with minimum redundancy is discussed. The algorithm has been tested on ISCAS'85 bench mark and other circuits. The results show considerable improvement in the technology mapping with respect to area optimization of the circuit minimized redundancy.