Single Clock Diode Based Adiabatic Logic Family at Sub-90nm Regime

机译：低于90nm制程的基于单时钟二极管的绝热逻辑系列

获取原文

页面导航

著录项
相似文献
相关主题

著录项

来源
《International conference on computer science, electronics and engineering》|2019年|245-259|共15页
会议地点 Kuala Lumpur(MA)
作者
Sagar Jain; Neeta Pandey;
展开▼
作者单位

Department of Electronics and Communication Engineering Delhi Technological University Shahbad Daulatpur Main Bawana Road Delhi 110042 India;

展开▼
会议组织
原文格式 PDF
正文语种
中图分类
关键词
Adiabatic logic; SC-DBAL; Logic gates; TANNER EDA tools;

机译：绝热逻辑; SC-DBAL;逻辑门TANNER EDA工具;

相似文献

外文文献
中文文献
专利

1. Dual-rail improved adiabatic pseudo-domino logic with auxiliary clock: a low-power partially-adiabatic CMOS logic family [J] . W. M. Tan, K. T. Lau Microelectronics international: Journal of ISHM--Europe, the Microelectronics Society--Europe . 2003,第2期

机译：具有辅助时钟的双轨改进的绝热伪多米诺逻辑：低功耗部分绝热CMOS逻辑系列
2. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply [J] . Maksimovic D., Oklobdzija V.G. IEEE transactions on very large scale integration (VLSI) systems . 2000,第4期

机译：具有集成单相电源时钟电源的时钟CMOS绝热逻辑
3. Clocked CMOS adiabatic logic with integrated single-phasepower-clock supply [J] . Maksimovic D., Oklobdzija V.G., Nikolic B., IEEE transactions on very large scale integration (VLSI) systems . 2000,第4期

机译：具有集成单相电源时钟电源的时钟CMOS绝热逻辑
4. Single Clock Diode Based Adiabatic Logic Family at Sub-90nm Regime [C] . Sagar Jain, Neeta Pandey International conference on computer science, electronics and engineering . 2020

机译：基于SUB-90NM制度的单钟代二极管基于绝热逻辑系列
5. Extra low power, single clock power adiabatic circuit logic. [D] . Shih, Chih-Kuang. 2002

机译：超低功耗，单时钟功率绝热电路逻辑。
6. All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal [O] . Cheng-Yu Wang, Chun-Wei Chen, Hung-Chang Jau, -1

机译：基于各向异性非线性响应液晶的全光晶体管和二极管作用及逻辑门
7. Low-voltage single-phase clocked quasi-adiabatic pass-gate logic family for low-power submicron VLSI CMOS applications [O] . Loo Edward K. W. 2007

机译：适用于低功耗亚微米VLSI CMOS应用的低压单相时钟准绝热传递门逻辑系列
8. A Switching-Diode Clock-Pulse Generator (Cpg) to Supply Three-Clock-Cycle Magnetic Logic Elements [R] . Kivenko, S. T., Parylis, M. E., Svidler, K. P. 1970

机译：开关二极管时钟脉冲发生器（Cpg），用于提供三个时钟周期的磁逻辑元件

Single Clock Diode Based Adiabatic Logic Family at Sub-90nm Regime

著录项

相似文献

相关主题

期刊订阅