A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output

摘要

Circuit designing of variable delay elements has been in practice for decades. However, these delay circuits have not been able to demonstrate equal rise and fall delays at its output. One of the major reasons for this failure is that the construction of delay circuits is non-symmetric. In this paper, we have attempted in designing a simple symmetric architecture which can produce the delayed output with almost identical rise and fall time. The proposed delay circuit is simulated using 90 nm GPDK in Cadence Virtuoso® initially for an input signal of 1 GHz at power supply Vdd = 11 V and the results infer that the contrast (A) in rise and fall time is very small even during the input variations.