Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique

摘要

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold - high V_(th) for good standby power and low V_(th) for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.