首页> 外文会议>IEEE International Conference on Solid-State and Integrated Circuit Technology;ICSICT-2012 >A more CMOS process compatible scheme to tune the Schottky Barrier Height of NiSi to electrons by means of dopant segregation (DS) technique
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A more CMOS process compatible scheme to tune the Schottky Barrier Height of NiSi to electrons by means of dopant segregation (DS) technique

机译:通过掺杂隔离(DS)技术将CMOS工艺兼容的方案将NiSi的肖特基势垒高度调整为电子

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) by means of boron (B) dopant segregation (DS) technique is presented. This scheme consists of the following steps: (1) deposit Ni layers on Si substrate; (2) rapid thermal anneal (RTA1) at 300°C/60 s to form Ni-rich silicide followed by un-reacted Ni strip; (3) implant B ions into preformed Ni-rich silicide; (4) RTA2 at 450–700 °C/30 s to transform Ni-rich silicide to NiSi and to induce B DS at NiSi/Si interface as well. The φ
机译:)借助于硼(B)提出了掺杂剂分离(DS)技术。该方案包括以下步骤:(1)在Si衬底上沉积Ni层; (2)300°C / 60 s的快速热退火(RTA1),形成富镍硅化物,然后进行未反应的镍带; (3)将B离子注入预先形成的富Ni硅化物中; (4)在450-700°C / 30 s的RTA2可以将富镍硅化物转化为NiSi,并在NiSi / Si界面处诱导B DS。 φ

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