A Low Power Signal Acquisition Channel with a Novel Systematic Power Minimization Scheme

摘要

This paper implements an analog front-end with a proposed systematic power minimization scheme to reduce both the analog front-end power consumption and the data converter consumption without any performance degradation. The scheme creatively uses intensive pulse signals from a counterbased digital control circuits in a SAR ADC to finely tune up/down the amplifier output driving ability. The amplifier's output stage is configurable and divided into several slices in parallel. Each output slice can be individually controlled by the control signal from ADC. The paper implements the systematic power minimization scheme with an 8-bit SAR ADC and a configurable amplifier. The simulation results verify the correctness and effectiveness of the proposed scheme.