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Design of Small Area and Low Power Consumption Mask ROM

机译:小面积低功耗掩模ROM的设计

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The compact full custom layout design of a 16-Kb mask-programmable CMOS ROM with low power dissipation is introduced in this paper. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 PJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 um 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, not only the layout design can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.
机译:本文介绍了一种低功耗的16 Kb掩模可编程CMOS ROM的紧凑型全定制布局设计。通过优化存储单元的尺寸和外围电路结构,ROM具有0.050 mm2的小面积,在+1.8 V时的功率延迟积为0.011 PJ / bit。通过以下方法,可以实现高封装密度和出色的功率延迟积使用中芯国际0.18 um 1P6M CMOS技术。提出了一种新颖且简单的读出放大器/驱动器结构,该结构可有效恢复信号全摆幅,并将信号上升时间减少2.4 ns,并减少存储器访问时间。 ROM具有8.6 ns的快速访问时间。结果,不仅可以将布局设计作为其程序存储器嵌入到微处理器系统中,而且可以作为ROM ASIC单独制造。

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