Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

摘要

In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-uA range and overall 1200X leakage reduction including process, circuit and system optimization.