Accurate chip level timing analysis requires a careful modeling of interaction between logic drivers and interconnect wires. Existing static-timing analysis methodologies translate the actual loading and interconnect parasitics into a single effective capacitance. However, previous approaches to perform that translation capture the delay information only. They are not able to capture the slew information at the output of logic drivers, which results in unnecessary inaccuracy for static timing analysis. This paper presents a new accurate and simple closed form approach to compute the effective capacitance and model the slew rate at the signal output more accurately. Our approach is especially suitable for the chip level timing analysis at the early stage of design.
展开▼
