A Novel VLSI Divide and Conquer Array Architecture for Vector-Scalar Multiplication

摘要

A novel VLSI array architecture for vector-scalar multiplication is introduced. It is based on a parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. Two variations of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), namely PVSMA-A and PVSMA-AT, are implemented and compared to the parallel implementation with carry-save array multipliers. PVSMA-A is optimized for area (A), and is shown to achieve significant area (A) savings at the cost of increased operational delay (T). PVSMA-AT is optimized for area-time product (AT), and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings.