School of Information, South China Agricultural University,Guangzhou 510642,School of Information Engineering, Jiangxi University of Science and Technology, Ganzhou 341000, China Department of (地址未取全);
School of Information Engineering, Jiangxi University of Science and Technology,Ganzhou 341000, China;
Department of Chemical and Petroleum Engineering, Schulich School of Engineering,University of Calgary, Calgary, AB T2N 1N4, Canada;
Institue of Automation,Chinese Academy of Sciences, Beijing 100190, China;
Evolvable hardware super-high dimension equations group; FPGA hardware/software Codesign; systolic array;
机译:基于FPGA的可演化硬件芯片求解超高维方程组的研究
机译:基于FPGA的基于FPGA的硬件架构,用于基于局部微分方程的模糊均匀增强
机译:基于可重新配置的六角形的Systolic阵列架构,用于FPGA上的可进化硬件
机译:基于FPGA的可再现硬件芯片解决超高尺寸方程组
机译:基于FPGA的体系结构的开发,可以在硬件中实现三维有限差分时域算法,以分析电磁传播。
机译:使用深度学习求解高维偏微分方程
机译:基于FpGa的可演化硬件芯片求解超高维方程组的研究