Interfacing a Verification, Validation, and TestingProcess Model with Product Development Methods

摘要

A thorough balancing of the costs of conducting verification and validation withrnthe costs of failure promises new possibilities in reducing overall project costs and time-tomarket.rnOne goal of the presented SysTest project is to develop an approach to support thernstrategic verification, validation, and test (VVT) planning. This approach, reflected in the VVTrnProcess Model, supports the trade off between different VVT strategies by calculating the effectrnof the strategy on cost-, schedule-, and quality-risk. This paper describes the VVT ProcessrnModel, which is currently developed, and its application in the development process of arnhydraulic pump. Furthermore, its interfaces with other company methods and the correspondingrninformation flows between them are illustrated. To demonstrate its potential, the VVT ProcessrnModel is positioned in the verification process.