A System Theoretic Framework for VV

摘要

This paper begins with a discussion of thernmeaning of the words validation and verification in thernsystems engineering context; what should be validated,rnwhat should be verified and when. The systemrntheoretic framework proposed for V&V is thenrndescribed featuring the mathematical structure of thernsystem test requirement. Finally, the specific V&Vrntasks are defined within the system theoreticrnframework.