Integrated Simulation of Line-Edge Roughness (LER) Effects on Sub-65 nm Transistor Operation: From Lithography Simulation, to LER Metrology, to Device Operation

摘要

Understanding how CD metrology, lithographic material and processing, affect linewidth roughness (LWR), and finally device operation is of immense importance in future scaled MOS transistors. The goal of this work is to determine the impact of spatial LWR parameters as well as the relative importance of LWR and CD variation on device operation and to connect material and process parameters with these effects. To this end, we examine first the impact of LWR on threshold voltage shifts by using model lines with fractal self-affine characteristics for the simulation of transistor gate morphology. It is found that for resist lines or transistor gates with constant sigma LWR σ_(LWR), the decrease of spatial LWR parameters (correlation length ξ and roughness exponent α) leads to smaller deviations from the designed electrical transistor performance. Second, the effects of photoresist polymer length and acid diffusion length on LWR parameters and transistor performance are investigated. Through the application of a homemade simulator of the lithographic process, it is shown that photoresists with small polymer chains and small acid diffusion lengths form lines with low LWR parameters (r.m.s. LWR σ_(LWR), ξ, α) and thus lead to transistors with more reliable electrical performance. Furthermore, the related problem of the relative importance of CD variation and LWR on device operation is addressed. We confirm and generalize the findings of previous works according to which CD variation has more drastic effects on threshold voltage shift than LWR.