Gate Tie-Down construct in the 22FDX~(™) Technology: a silicon-based method for Layout Optimization

摘要

In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX™, novel Middle-of-Line (MOL) constructs have been specifically enabled. The Gate Tie-Down (or "continuous RX") construct allows an optimal device performance without loss of area. A method for a silicon-based evaluation and optimization of the Gate Tie-Down construct is presented here. We discuss the main design-process failure modes, their severity and the risk mitigation options. A full-factorial Design of Experiment used for the construct validation is presented and analyzed. Two critical failure modes are isolated and discussed. As a final step, the optimized design is validated over a much larger number of occurrences, showing a robust 4-sigma manufacturing design margin.