Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node

摘要

The Fin-FET Technology scaling to sub 7nm node, using 193 immersion scanner is restricted due to reduced margins for process. The cost of the process and complexity of designs is increasing due to multi-patterning to achieve area scaling using 193i scanner. In this paper, we propose a two Fin-cut mask design for Fin-pattering of 112 SRAM (two Fins for pulldown and one Fin for pull-up and pass-gate device) cell using 193i lithography and its comparison with EUVL single print. We also propose two keep masks for middle of line patterning ,with increased height of the SRAM cell using 193i, that results in area of a uniform-Fin SRAM cell area at 7nm technology; whereas EUVL can enable non-uniform SRAM cell at reduced area. Due to unidirectional patterning, margins for VIAO landing over MOL are drastically reduced at 42nm gate pitch and hence to improve margins, the orientation for 1st metal is proposed to be orthogonal to the gate. This results in improved performance for SRAM and reliability of the technology.