首页> 外文会议>Conference on Photonic Devices and Algorithms for Computing Ⅲ Jul 29-30, 2001, San Diego, USA >Optical Multi-Token-Ring Networking Using Smart Pixels With Field Programmable Gate Arrays (FPGAs)
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Optical Multi-Token-Ring Networking Using Smart Pixels With Field Programmable Gate Arrays (FPGAs)

机译:使用具有现场可编程门阵列(FPGA)的智能像素的光学多令牌环网络

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This research explores architectures and design principles for monolithic optoelectronic integrated circuits (OEICs) through the implementation of an optical multi-token-ring network testbed system. Monolithic smart pixel CMOS OEICs are of paramount importance to high performance networks, communication switches, computer interfaces, and parallel signal processing for demanding future multimedia applications. The general testbed system is called Reconfigurable Translucent Smart Pixel Array (R-Transpar) and includes a field programmable gate array (FPGA), a transimpedance receiver array, and an optoelectronic very large-scale integrated (OE-VLSI) smart pixel array. The FPGA is an Altera FLEX10K100E chip that performs logic functions and receives inputs from the transimpedance receiver array. A monolithic (OE-VLSI) smart pixel device containing an array of 4 X 4 vertical-cavity surface-emitting lasers (VCSELs) spatially interlaced with an array of 4 X 4 metal-semiconductor-metal (MSM) detectors connects to these devices and performs optical input-output functions. These components are mounted on a printed circuit board for testing and evaluation of integrated monolithic OEIC designs and various optical interconnection techniques. The system moves information between nodes by transferring 3-D optical packets in free space or through fiber image guides. The R-Transpar system is reconfigurable to test different network protocols and signal processing functions. In its operation as a 3-D multi-token-ring network, we use a specific version of the system called Transpar-Token-Ring (Transpar-TR) that uses novel time-division multiplexed (TDM) network node addressing to enhance channel utilization and throughput. Host computers interface with the system via a high-speed digital I/O board that sends commands for networking and application algorithm operations. We describe the system operation and experimental results in detail.
机译:本研究通过实现光学多令牌环网络测试平台系统,探索了单片光电集成电路(OEIC)的体系结构和设计原理。单片智能像素CMOS OEIC对于高性能网络,通信交换机,计算机接口和并行信号处理,对于要求苛刻的未来多媒体应用至关重要。通用测试平台系统称为可重新配置的半透明智能像素阵列(R-Transpar),包括一个现场可编程门阵列(FPGA),一个跨阻接收器阵列以及一个光电超大规模集成(OE-VLSI)智能像素阵列。 FPGA是Altera FLEX10K100E芯片,它执行逻辑功能并从跨阻接收器阵列接收输入。包含4 X 4垂直腔表面发射激光器(VCSEL)阵列的单片(OE-VLSI)智能像素设备在空间上与4 X 4金属-半导体-金属(MSM)检测器阵列交错排列,并与这些设备连接,执行光学输入输出功能。这些组件安装在印刷电路板上,用于测试和评估集成的单片OEIC设计以及各种光学互连技术。该系统通过在自由空间中传输3-D光学数据包或通过光纤映像向导在节点之间移动信息。 R-Transpar系统可重新配置以测试不同的网络协议和信号处理功能。在其作为3-D多令牌环网络的操作中,我们使用称为Transpar-Token-Ring(Transpar-TR)的系统的特定版本,该版本使用新颖的时分多路(TDM)网络节点寻址来增强信道利用率和吞吐量。主机通过高速数字I / O板与系统连接,该I / O板发送用于网络和应用算法操作的命令。我们详细描述了系统的操作和实验结果。

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